Dual damascene is currently being used in sub-0.25 micron logic and 1-gigabyte dynamic random access memory (DRAM) cells and beyond technologies to reduce cost of ownership and improve via reliability. In addition, copper wiring is employed in sub-0.25 micron generation back end of the line (BEOL) wiring to reduce the wiring resistance and to meet the BEOL resistance capacitance (RC) delay performance requirements. The initial CMOS programs used SiO.sub.2 as a dielectric material. However, as chip function integration increases, back end wiring densities also increase. Because of this, there exists a greater need for intralevel insulators having a dielectric constant lower than Sio.sub.2. SiO.sub.2 is presently the insulator of choice since the same has relatively good film properties.
The incorporation of low dielectric materials into wiring structures is crucial in order to reduce delays due to cross-talk and stray capacitance. Presently used SiO.sub.2 has a relative dielectric constant of about 4, which limits its use because of potential cross-talk and RC delays.
Subsequent technologies will use dielectrics that have a lower dielectric constant than SiO.sub.2 to reduce wiring capacitance and overall chip delay. In the past, integration of damascene structures into low dielectric constant materials has been difficult or nearly impossible due to the relatively poor film properties, e.g. hardness, adhesion, stability and stress, or the difficulty in the anisotropic etching of low dielectric constant dielectrics compared with SiO.sub.2.
In view of the problems associated with integrating low dielectric constant dielectrics into damascene structures, there remains a need for providing a simple, yet effective method of fabricating damascene structures which contain a dielectric material, i.e. insulator, that has a lower dielectric constant than SiO.sub.2. Such a method would eliminate the integration problems normally encountered in fabricating damascene wiring structures.